1. Field of the Invention
The present invention relates to a semiconductor integrated circuit layout method and apparatus as well as a semiconductor integrated circuit and in particular, to a layout method and apparatus using a primitive cell.
2. Description of the Related Art
In a semiconductor integrated circuit layout design using primitive cells, among basic (minimum) cells (called xe2x80x98Primitive cellsxe2x80x99) constituting transistors and logical gates, primitive cells having required functions are selected and electrically connected to one another to design a semiconductor integrated circuit layout. This layout design is performed by using a computer or the like.
FIG. 5 shows a layout example of a layout design using primitive cells (also called xe2x80x98standard cellsxe2x80x99).
As shown in FIG. 5, the primitive cells have no region for arranging a signal line (called xe2x80x98inter-cell signal linexe2x80x99) for electrical connection between core portions of the primitive cells. The inter-cell signal line for electrical connection between the primitive cells is wired in a wiring region between rows where the primitive cells are arranged.
In an ordinary semiconductor integrated circuit, because of its configuration, the inter-cell signal line intersects a power source wiring, and the wiring for an inter-cell signal line and wiring for a power source are performed over a plurality of layers. A contact is arranged for a connection point of the wiring performed over a plurality of layers.
The inter-cell connection signal line electrically connecting primitive cells is arranged over a plurality of layers, requiring a contact. Accordingly, the inter-cell connection signal line arrangement is restricted, increasing the wiring region area. As a result, it has been impossible to reduce the entire layout area of a semiconductor integrated circuit.
That is, in order to reduce the layout area and increase the element density, it is necessary to reduce the wiring region area. For example, Japanese Patent Publication 6-169016 discloses a primitive cell type layout design method for reducing the semiconductor integration degree. As shown in FIG. 6(a) and in FIG. 6(b), among a plurality of primitive cells, a first and a second primitive cell each having a logic portion to be electrically connected to each other, have a wiring region for electrical connection between the logic portions and the power source.
However, in the layout method disclosed in the aforementioned publication, there is only a single arrangement of inter-cell connection signal lines, i.e., there is only one selection of the number of grids. Accordingly, it is impossible to optimize the number of grids of primitive cells according to a target circuit. As a result, it is impossible to minimize the layout area.
It is therefore an object of the present invention to provide a semiconductor integrated circuit device enabling selection of primitive cell groups having different numbers of grids so as to minimize the layout are, and a layout design method and a layout design apparatus.
The semiconductor integrated circuit device according to the present invention includes a plurality of primitive cells connected electrically,
each primitive cell being constituted by a core portion having an electric circuit for realizing a function inherent to the primitive cell and a power supply wiring portion for electrical connection between the core portion and a predetermined power supply wiring and between different primitive cells,
wherein the power supply wiring portion has such a configuration that an optimal number of wires is selected for electrical connection between core portions of respective primitive cells.
Moreover, the layout method of a semiconductor integrated circuit according to the present invention is a layout method of a semiconductor integrated circuit including primitive cells, each constituted by a core portion having an electric circuit for realizing a function inherent to the primitive cell and a power supply wiring portion for electrical connection between the core portion and a predetermined power supply wiring and between different primitive cells, said layout method comprising steps of:
storing in a storage unit a plurality of primitive cells having an identical core function and different number of inter-cell signal lines are defined as a primitive cell small group, and
selecting and allocating a primitive cell having an appropriate number of inter-cell signal lines allocatable as a power supply wiring portion